The present invention relates to a semiconductor integrated circuit device which matches the trend toward further miniaturization and to a method for designing the same.
If a plurality of functional blocks are formed in one chip, it has not been performed conventionally to provide MOS transistors contained in a plurality of digital functional circuit blocks with different gate lengths or provide the respective gate oxide films of the MOS transistors with different thicknesses.
In an analog circuit or a circuit for which consideration should be given to a latch-up or a breakdown voltage caused by an electrostatic damage (ESD), it has been conventional practice to use different design rules for a transistor provided on the I/O pad portion of the circuit and for the logic portion of the circuit. This is because different power supply voltages are applied thereto.
On the other hand, it has not been performed to use different design rules for process design within one digital functional block or one analog functional block.
It has not been performed, either, to form chips from one wafer by using different masks, form chips with different sizes or different functions from one wafer, or fabricate various chips designed to have different performances from one wafer.
As design sizes are reduced increasingly year after year, however, a chip designing process performed by using one layout design rule for one chip encounters the following problems.
The layout design rule which is 0.13 μm in the year 2001 is expected to become 0.10 μm in the year 2005. If design is to be performed in accordance with the layout design rule of 0.10 μm, a fabrication process requires a patterning accuracy on the order of several tens of nanometers.
In that case, it will become extremely difficult to control variations in patterning accuracy dependent on the regions (portions) of the principal surface of a wafer, i.e., an amount of process variation to several tens of nanometers by considering each of variations in patterning accuracy in the fabrication process, the relationship between the regions (portions) of one chip and layout densities therein, and the like.
If a design rule also considering variations in patterning accuracy is used, a design margin is reduced dramatically so that the yield rate is reduced significantly. As a consequence, the trend toward further miniaturization drastically increases the manufacturing cost for a chip.